An edge-triggered flip-flop is a component frequently employed in microelectronics for storing a binary value or “state”. This device is often formed by assembling two “latch” circuits together, which are referred to as master and slave. A latch circuit is a bistable structure composed of two inverters connected such that the output of the first inverter is fed back to its input via the second inverter. One of these inverters can be an inverter of the tri-state type.
The edge-triggered flip-flop has two distinct periods: a transparent period over a short time window around an edge of the clock signal; and an opaque or storage period lasting for the remainder of the time of the period, and in which the output of the flip-flop delivers the last information to pass through it during its preceding transparent state.
In the case of a flip-flop triggered on a rising edge, the first latch circuit is transparent when the clock signal is in the low state and opaque when the clock signal is in the high state. The second latch circuit is transparent when the clock signal is in the high state and opaque when the clock signal is in the low state. Thus, the resulting flip-flop is transparent during the rising edge of the clock signal.
The two latch circuits, master and slave, are connected in series via a switch. The switch can be conventionally formed in two ways: an inverter of the tri-state type composed of four transistors in series, two p-MOS transistors and two n-MOS transistors; or a switch of the pass-gate type composed of two transistors in parallel, one p-MOS transistor and one n-MOS transistor.
An edge-triggered flip-flop also comprises two feedback loops, where the outputs of the master and slave inverters are fed back to their respective inputs, and two power supplies, one main power supply being discontinuous and the other continuous. The feedback loops allow the states to be stored during a first mode, or active mode, in other words when the inverters are powered. In addition, the flip-flop comprises a retention means that allows the state of the flip-flop input data to be stored in an “inactive” mode, in other words when the main power supply is interrupted.
A first example of this type of flip-flop is the MTCMOS circuit described in the article “MTCMOS with outer feedback flip-flops,” IEEE 2003 (Mircea R. Stan et al.).
A second example relates to flip-flops known as “balloon storage loop flip-flops” described in the article “A 1V high-speed MTCMOS circuit scheme for power-down application circuits,” IEEE Journal of Solid State Circuits, Vol. 32, No. 6, June 1997 (Satoshi Shigematsu).
These existing devices are based on either the duplication of a latch circuit within the flip-flop, or the re-use of certain transistors in the flip-flop that are associated with switches, so as to construct an externally coupled inverter capable of storing the state. These devices require a large number of components and hence are relatively costly to produce.